Agilent Technologies N4962A Guia do Utilizador descarregar pdf (Página 47)

Operation

Serial BERT 12.5 Gb/s User Guide 47

The Pat TrigO connector is an output pattern trigger from the PRBS generator.

The Pat TrigO signal changes state after 32 complete PRBS bit streams have

been generated. Pat TrigO has a frequency equal to (clock_rate) / (32 *

bit_pattern_length); With a clock speed of 10 GHz, the Pat TrigO frequency is

2.4 MHz with a pattern length of 2

-1, and 0.15 Hz with a pattern length of

-1.

TX CKI and RX CKI are the transmit (PRBS generator) and receiver (error

detector) clock inputs. To use an external 500 Mb/s to 12.5 Gb/s clock signal,

connect the external clock to both TX CKI and RX CKI, as described in Sections

3.4 and 3.5, respectively.

TX CKO and RX CKO are the internal clock output ports. These are connected to

TX CKI and RX CKI when the internal clock is used to trigger the PRBS

generator and error detector. The clock output ports are detailed in

Section 3.3.

HF TrigO and LF TrigO are clock trigger outputs from the internal clock system,

detailed in Section 3.3.

Ext CKI is a low-frequency 1/16th-rate clock input used when synchronizing

the internal clock system with a LF external signal. The Ext CKI port is detailed

in Section 3.3.

JitterI is a DC-100 MHz input that is FM modulated onto the TX CKO and HF

TrigO clock. A sinusoid should be applied to the input port, and the resulting

PRBS output jitter will be proportional to the sinusoid amplitude. This is

detailed in Section 3.3.

The GPIB connector and 5-bit address switch is accessible from the rear panel.

All GPIB devices on the same GPIB bus must have different addresses to

function together. GPIB devices are programmed by referencing the address of

the device, as well as the bus type. This is detailed in Section 5. The factory

default address is 25.

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Agilent Technologies N4962A Guia do Utilizador Página 47