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N4962A System Overview

Serial BERT 12.5 Gb/s User Guide 17

2 N4962A System Overview

The N4962A consists of three functional blocks:

• Internal/external clock system with analog jitter injection

• PRBS generator (TX) with variable output amplitude control

• Error detector (RX) with electronic clock phase adjustment

The N4962A is controlled by front-panel buttons and remote GPIB (IEEE 488.2)

commands; information is conveyed with LED indicators and a display on the

front panel, along with GPIB data communication.

Figure 2. N4962A simplified block diagram; system overview

The clock system features an internal generator that creates a 9.85 to

11.35 GHz system clock from an internal 1/16

-rate clock generator. The

internal clock/16 can also be phase locked to an external 1/16

clock if

desired. The high-frequency TX clock and trigger output can be FM-modulated

with an optional external jitter signal. Alternatively, external 500 Mb/s to

12.5 Gb/s clocks can be used in place of the internal high-frequency clocks for

the PRBS generator and error detector.

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Agilent Technologies N4962A Guia do Utilizador Página 17