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System Details and Performance Specifications

Serial BERT 12.5 Gb/s User Guide 29

The PRBS bit stream consists of data generated by one of five patterns, listed

in Table 7. The pattern length is a system configuration setting, selected by

changing the Config State “PAT xxxx” setting, detailed in Section 4.2.3.

Table 7. N4962A PRBS generator patterns

Pattern

Config State

Polynomial

Tone Spacing (10Gb/s)

ITU Standard

– 1

2E31

+ X

+ 1 = 0

4.67

ITU

-T 0.150

– 1

2E23

+ X

+ 1 = 0

1.19 kHz

ITU-T 0.150

– 1

2E15

+ X

+ 1 = 0

305 kHz

ITU-T 0.150

– 1

2E7

+ X

+ 1 = 0

78.7 MHz

ITU-T V.29

3.5 Error Detector

The error detector counts errors in the input bit stream, based on the

configuration settings and the RX CKI input clock rate. The internal clock can

be used for 9.85 to 11.35 Gb/s operation, or an external clock can be used for

500 Mb/s to 12.5 Gb/s operation. The PRBS generator and error detector must

be clocked at the same rate.

The error detector samples the input bit stream on the rising edge of the clock.

If the clock transition occurs near the data transition – that is, if the clock and

the data are changing at the same time – the sampled data value is uncertain,

which may result in high BER. This is illustrated in Figure 13.

To ensure the clock and data transition points are correctly offset, the error

detector features a user-adjustable 360-degree electronic phase shifter. The

phase shifter delays the clock input to the detector, allowing the user to select

the optimal sampling point. The N4962A can automatically adjust the receiver

phase to the best sampling point, detailed in Section 4.6.

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