Table 2: Output characteristics for J-BERT N4903A generator. All
timing parameters are measured at ECL levels.
Range of operation 150 Mb/s to 12.5 Gb/s (opt. C13)
Can be programmed up to
13.5 Gb/s
150 Mb/s to 7 Gb/s (opt. C07)
< 620 MHz only with external
clock
Frequency accuracy ± 15 ppm typical
Format NRZ, normal or inverted
Amplitude/resolution 0.10 V to 1.8 V, 5 mV steps
Addresses LVDS, CML, PECL,
ECL (terminated to 1.3 V/
0 V/-2 V), low voltage CMOS
Output voltage window -- 2.0 V to +3.0 V
Predefined levels ECL, PECL (3.3 V), LVDS, CML
Transition times
(20% to 80%) < 20 ps
(10% to 90%)
1)
< 25 ps
Jitter 9 ps pp typical with disabled jitter
sources and internal clock
Clock/data delay range ± 0.75 ns in 100 fs steps
External termination -- 2 V to +3 V
voltage
2)
Crossing point Adjustable 20% to 80% typical to
emulate duty cycle distortions
Single error inject Adds single errors on demand
Fixed error inject Fixed error ratios of 1 error in
10
n
bits, n = 3, 4, 5, 6, 7, 8, 9
Interface
3)
Differential or single-ended,
DC coupled, 50W
Connector 2.4 mm female
1)
At 10 Gb/s and 7 Gb/s
2)
For positive termination voltage or termination to GND, external
termination voltage must be less than 3 V below VOH. For
negative termination voltage, external termination voltage must
be less than 2 V below VOH. External termination voltage must
be less than 3 V above VOL.
3)
Unused outputs must be terminated with 50W to GND.
J-BERT N4903A High-Performance Serial BERT Data Sheet
Figure 12: Clean output signal. 10 Gb/s, LVDS levels.
Figure 13: Pattern generator setup screen with graphical
display of signal levels.
Figure 11: Generator connectors on front panel
Data output (DATA OUT)
Pattern Generator Specifications
7
Pattern generator key characteristics:
• Available as 7 and 12.5 Gb/s pattern generator with-
out error detector (opt. G07 and G13)
• Differential outputs for data, clocks and trigger
• Variable output voltages covering LVDS, ECL, CML
• Transitions times < 20 ps
• Clean pulses with jitter < 9 ps pp
• High precision delay control input to inject jitter from
an external source
• Calibrated and integrated jitter injection
(options J10, J20, both retrofitable)
• Subrate clocks for generating any reference clock
• Pattern sequencing and 32 Mbit pattern
• SSC clocks for computer buses (option J11)
Specifications-Pattern Generator
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