Table 13: Specification for the clock input
Frequency range 150 MHz to 12.5 GHz
(option C13)
150 MHz to 7 GHz
(option C07)
Amplitude 100 mV to 1.2 V
Sampling Positive or negative
clock edge
Interface AC coupled, 50 W nominal
Connector SMA female
Table 12: Specifications for error detector
Range of operation 150 Mb/s to 12.5 Gb/s
(opt. C13)
150 Mb/s to 7 Gb/s
(opt. C07)
Format NRZ
Maximum input amplitude 2.0 V
Termination voltage
1)
-- 2 V to +3 V or off
(true differential mode)
Sensitivity
2)
< 50 mV pp
Intrinsic transition time
3)
25 ps typical 20% to 80%,
single ended
Decision threshold range --2 V to +3 V in 1 mV steps
Maximum levels --2.2 V to +3.2 V
Phase margin
4)
1 UI – 12 ps typical
Clock/Data sampling delay ± 0.75 ns in 100 fs steps
Interface Single-ended: 50 W nominal,
Differential: 100 W nominal
Connector 2.4 mm female
1)
Selectable 2V operating voltage window, which is in the
range between --2.0 V to +3.0 V. The data signals, termination
voltage and decision threshold have to be within this voltage
window.
2)
At 10 Gb/s, BER 10
-12
, PRBS 2
31
-1.
3) At cable input, @ ECL levels
4)
Based on the internal clock.
10 J-BERT N4903A High-Performance Serial BERT Data Sheet
Figure 16: Front panel connectors for error detector
Data inputs (DATA IN)
Clock inputs (CLK IN)
The error detector requires an external clock
signal to sample data or it can recover the clock
from the data signal using the built-in clock data
Error detector key characteristics:
• True differential inputs to match today’s ports
• Built-in CDR for clockless data
• Auto-alignment of sampling point
• Bit recovery mode for unknown data traffic
(option AO1)
• Burst mode for testing recirculation loop
• BER result and measurement suite
• Quick eye diagram and mask with BER contours
• Pattern capture
• CDR with tunable loop bandwith (option CTR)
Clock data recovery
The error detector can recover the clock from the
incoming data stream with the built-in clock data
recovery (CDR). The CDR with fixed loop band-
width is included in options C07 and C13. The
tunable loop bandwidth is available with N4903A
option CTR. For upgrading an existing J-BERT to
the compliant and tunable CDR loop bandwidth
option UTR is available.
The recovered clock signal is available at the aux
output.
Table 14: Specifications for the clock data recovery (options C07,
C13, CTR, UTR)
Input data rate
3)
1 Gb/s to 12.5 Gb/s
1)
(option C13)
1 Gb/s to 7 Gb/s (option C07)
CDR clock output jitter 0.01 UI rms (RJ) typical
2)
Fixed loop bandwidth data rate: 1667; see figure 17
1)
With bit recovery mode (option A01) enabled the max. data rate
is 11.5 Gb/s.
2)
When measured with PRBS 2
23
-1
3)
For J-BERTs with serial number DE45Axxxxx which have not
been upgraded to option UTR, the CDR operates in these ranges
(loop bandwidth):
9.20 Gb/s to 11.32 Gb/s (8 MHz)
4.23 Gb/s to 6.40 Gb/s (4 MHz)
2.115 Gb/s to 3.20 Gb/s (2 MHz)
1.058 Gb/s to 1.60 Gb/s ( 1MHz)
Specifications-Error Detector
Error Detector Specifications
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