Available J-BERT configurations
BERT pattern generator and error detector,
including built-in CDR
BERT 150 Mb/s to 12.5 Gb/s N4903A-C13
BERT 150 Mb/s to 7 Gb/s N4903A-C07
Pattern generator (PG) options
*only in combination with -J10
PG 150 Mb/s to 12.5 Gb/s* N4903A-G13
PG 150 Mb/s to 7 Gb/s* N4903A-G07
SSC clocking* N4903A-J11
Jitter tolerance options
RJ, PJ, SJ, BUJ injection N4903A-J10
ISI and sinusoidal N4903A-J20
interference injection
Jitter tol. compliance suite N4903A-J12
Error detector options
Bit recovery mode N4903A-A01
Compliant CDR N4903A-CTR
with tunable loop bandwidth
Upgrades
All options upgradable (see page 17)
The J-BERT N4903A High-Performance Serial
BERT provides the only complete jitter tolerance
test. It is the ideal choice for R&D and validation
teams characterizing and stressing chips and
transceiver modules that have serial I/O ports up
to 7 Gb/s or 12.5 Gb/s. It can characterize a
receiver’s jitter tolerance and prove its compliance
to today’s most popular standards, such as PCI
Express, SATA, Fibre Channel, Fully Buffered
DIMM, CEI, 10 GbE/ XAUI and XFP/XFI.
Accurate characterization is achieved with clean
signals from the pattern generator, which features
exceptionally low jitter and extremely fast transi-
tion times. Test set-up time is reduced signifi-
cantly, because the J-BERT N4903A matches most
recent serial bus standards
optimally:
• Undeterministic patterns can now be analyzed
with the bit recovery mode.
•A pattern sequencer helps to set up training
sequences quickly, to get complex devices into
loop-back test mode.
• Reference clocks can be provided by the sub-
rate clock outputs, which can generate any ratio
of clock to data rate.
• All I/Os are differential and a built-in CDR
allows testing of clockless interfaces.
The J-BERT N4903A is a future proof serial
BERT platform, which is configurable for today’s
test and budget requirements but also allows
upgrades to all options and full speed.
Measurements
BER and measurement suite
• BERT scan
• Output timing jitter
• Spectral jitter decomposition
• Eye contour
• Quick eye diagram and BER contour
• Fast eye mask
• Output level and Q factor
• Error location capture
• Fast total jitter
• Pattern capture
Jitter tolerance tests
• Manual jitter composition (option J10)
• Automated jitter tolerance
• Characterization (option J10)
• Automated jitter tolerance compliance
(option J12)
Applications
• PCI Express
• SATA
• Fibre channel
• Fully buffered DIMM
• CEI
• 10 GbE/XAUI
• XFP/XFI
J-BERT N4903A High-Performance Serial BERT Data Sheet
3
J-BERT key characteristics:
• 150 Mb/s to 7 Gb/s or 12.5 Gb/s – enough margin for
characterizing today’s most popular serial interfaces
• Calibrated and integrated jitter injection (opt. J10).
All in one box: RJ, PJ, BUJ, ISI, sinusoidal interfer-
ence to stress the receiver with > 50 % eye closure
• Automated and compliant jitter tolerance tests covers
popular serial bus standards: PCI Express, SATA, Fibre
Channel, SATA, FB-DIMM, CEI 6G/11G, 10 GbE/XAUI,
XFP/XFI
• Delay control input for generator to apply any external
jitter source
• Bit recovery mode to test unknown data traffic
• Pattern sequencer to generate complex training
sequences
• SSC clocking for computer buses
• Subrate clocks to generate reference clocks easily
• Differential I/O for DATA and CLOCK and most supple-
mentary signals for testing serial interfaces
• Integrated CDR (clock data recovery) to test clock-
less devices from 1 to 12.5 Gb/s
• Compliant and tunable loop bandwidth (opt. CTR)
• Highest performance BERT for accurate
measurements
• Remote operation of GUI via web server
• All options retrofitable
J-BERT N4903A High-Performance Serial BERT
(482 páginas)
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