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Figure 22: Periodic jitter maximum for datarates ~ 3.375 Gb/s

using the 500 ps delay line.

J-BERT N4903A High-Performance Serial BERT Data Sheet

Periodic jitter (option J10)

This injects sinusoidal, rect-

angular or triangular jitter over

a wide frequency range.

Jitter Tolerance Test Specifications

The built-in jitter sources cover PCI Express,

SATA, Fibre channel, FB-DIMM, CEI 6 G/11 G,

10 GbE and XFP/XFI jitter tolerance test needs.

If jitter sources are enabled, the intrinsic jitter at

the pattern generators clock and data outputs is 1.4

ps rms typical.

Sinusoidal jitter (option J10)

This injects sinusoidal jitter in

the lower frequency range with

multiple UIs.

Figure 23: Sinusoidal jitter maximum UI

Figure 21: Periodic jitter maximum for all data rates using the

200 ps delay line.

Specifications-Jitter Tolerance Test

Table 20: Specifications for periodic jitter (PJ)

Range

0 to 200 ps pp @ all datarates

0 to 500 ps pp @ datarates

~ 3.375 Gb/s

Modulation 1 kHz to 300 MHz sinewave

frequency 1 kHz to 20 MHz triangle

1 kHz to 20 MHz square wave

Modulation frequency 0.5% ± 25 Hz typical

accuracy

Jitter amplitude 10% ± 1ps typical

accuracy

Signals impacted Data outputs: for all datarates

subrate clock outputs, for

datarates ~ 3.375 Gb/s when

using 500 ps delay line

Available range depends on modulation frequency and data rate

(see figure 18 and 19)

Table 21: Specifications for sinusoidal jitter (SJ)

Range

1000 UI @ 10 kHz

2 UI @ 5 MHz

For frequencies between 10 kHz

and 5 MHz the jitter amplitude

10 MHz

n x f (mod)

Modulation 100 Hz to 5 MHz

frequency (For higher modulation

frequencies see table 20 and 21.)

Modulation frequency 0.5% typical

accuracy

Jitter amplitude 2% ± 1ps typical

accuracy

Signals impacted Data and subrate clock outputs.

User selectable: all pattern gener-

ator outputs (data, clock, subrate

clock and trigger outputs.)

Available range depends on modulation frequency and data rate

(see figure 23).

1 2 ... 8 9 10 11 12 13 14 15 16 17 18

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