Development Flow for the Agilent 3070 Tester Without the PLD ISP Software Page 7
December 2010 Altera Corporation Using the Agilent 3070 Tester for In-System Programming in Altera CPLDs
Step 5: Compile the Executable Tests
Altera recommends using batch-driven compilation with either a BT-Basic or a UNIX
shell. Refer to the following batch file code in BT-Basic (assuming four executable tests
to program the target device and generation of debugging object code):
compile "digital/prog_a" ; debug
compile "digital/prog_b" ; debug
compile "digital/prog_c" ; debug
compile "digital/prog_d" ; debug
Save this file in the board directory to allow engineering changes to take place at a
later date. Refer to the corresponding shell script (the “–D” option generates
debugging information):
dcomp -D digital/prog_a
dcomp -D digital/prog_b
dcomp -D digital/prog_c
dcomp -D digital/prog_d
1 Compilation can be time-consuming, depending on the number of .pcf file vectors
contained in the source files, the type of controller, and controller loading. Altera
recommends using a batch file to automate the compilation of the ISP tests.
If you use a boundary-scan chain containing defined Altera devices, only the defined
Altera devices are programmed after the .pcf file vectors have been applied to the
JTAG interface.
Step 6: Debug the Test
After you have created the executable tests, you can debug the test system. The
applied vector set ensures that the device is correctly programmed by verifying the
contents of the device. The programming algorithm uses the TDO pin to check the
bitstream coming from the device. If any vector does not match the expected value,
the test fails, resulting in one of two scenarios:
■ The device ID does not match what is expected. This scenario is evident if the
failure occurs at the beginning of the first test.
■ The device programming failed.
You are not required to sift through each vector to determine the cause of the failure. If
the device fails to program, use the following troubleshooting guidelines:
■ Check the pull-down resistor in the test fixture. There may be pull-up resistors on
the board for the TCK pin. If the pull-down resistor is too large, the TCK pin may be
above the threshold of the device for a logic low. Adjust the value of the resistor
accordingly. For the specification on the input logic levels, refer to the appropriate
device family datasheet.
■ If an overpower error on the TCK pin occurs, check the value of the resistors
because they may be too low for the test system to back-drive for an extended
period of time.
■ Ensure that the test execution order is correct. If you execute the tests out of order,
the programming information will be incorrect. Also, if you execute the same test
twice in a row, the target device may be out of sequence and may not receive the
correct programming information.
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