Development Flow for the Agilent 3070 Tester Without the PLD ISP Software Page 3
December 2010 Altera Corporation Using the Agilent 3070 Tester for In-System Programming in Altera CPLDs
Step 1: Create a PCB and Test Fixture
The first step when using ISP is to properly layout your board and create the test
fixture.
Creating the PCB
The following recommendations highlight important areas of PCB design issues:
■ You must treat the
TCK
signal trace as carefully as a clock tree. TCK is the clock for
the entire JTAG chain of devices. These devices are edge-triggered on the
TCK
signal; therefore, you must protect this signal from high-frequency noise and
ensure good signal integrity. Ensure that the signal meets the pulse rise time (t
R
)
and pulse fall time (t
F
) parameters specified in the respective Device Family
Datasheet.
■ Add a pull-down resistor to the TCK signal. Hold the TCK signal low using a
pull-down resistor in-between the different pattern capture format (.pcf) file
downloads. Hold the TCK signal low because the Agilent 3070 drivers go into a
“high-Z” state in-between tests and briefly drive low when the next .pcf file is
applied. When the TCK line “floats”, the programming data stream is corrupted
and the device is not correctly programmed.
f For more information about .pcf file downloads, refer to “Step 2: Create a
.svf File”.
■ Provide VCC and GND test access points (TAPs) for the nails of the test fixture.
During operation, there must be enough TAPs to allow quiet PCB operation.
Having too few TAPs results in a noisy system that can disrupt the JTAG scans.
■ To reduce system noise, turn off the on-board oscillators. During programming,
on-board oscillators must have the ability to be electrically turned off.
■ Add external resistors to pull outputs to a defined logic level during
programming.
1 During programming, the output pins are tri-stated and are pulled up by a
weak internal resistor. However, Altera recommends forcing signals
requiring a pre-defined level to the appropriate level using an external
resistor.
f For more information about board design for ISP, refer to AN 100: In-System
Programmability Guidelines.
Creating the Fixture
For successful ISP, provide a clean interface between the test fixture and the target
board by using short wires in the test fixture to improve the TCK connection. Longer
wires can introduce inductive noise into the system that can disrupt programming.
Ensure the wire connecting TCK is not longer than one inch. Use the Agilent Fixture
Consultant software to manage the layout and creation of the test fixture (refer to the
Agilent Board Test Family Manual).
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