Agilent Technologies 42A Especificações

Agilent Technologies 16740/41/42A Logic AnalyzerService GuidePublication number 16740-97000December 2001For Safety information, Warranties, and Regula

10 Chapter 1: General InformationAccessories The following accessories are supplied with the 16740/41/42A logic analyzer.Mainframe and Operating Sys

100 Chapter 3: Testing PerformanceTo Test the Time Interval Accuracy2 Set up the Format tab. a In the Analyzer setup window, select the Format tab.

101Chapter 3: Testing PerformanceTo Test the Time Interval Accuracyg In the Pod Threshold window, select the Standard threshold voltage field. At th

102 Chapter 3: Testing PerformanceTo Test the Time Interval AccuracyConnect the logic analyzer1 Using a 6-by-2 test connector, connect channel 0 of

103Chapter 3: Testing PerformanceTo Test the Time Interval Accuracy3 Configure the Markers to measure the time interval. a In the Marker Setup windo

104 Chapter 3: Testing PerformanceTo Test the Time Interval Accuracye In the marker Setup window, select the Define... field associated with G2, and

105Chapter 3: Testing PerformanceTo Test the Multi-Card ModuleTo Test the Multi-Card ModuleThe multi-card test is only required for configured multi

106 Chapter 3: Testing PerformanceTo Test the Multi-Card ModuleSet up the logic analyzer1 Set up the Sampling tab. a In the Analyzer setup window, s

107Chapter 3: Testing PerformanceTo Test the Multi-Card Module3 Set up the Format tab. a Under one of the pod fields, select TTL.b In the Pod Thresh

108 Chapter 3: Testing PerformanceTo Test the Multi-Card Module4 Set up the Trigger tab.a In the Analyzer setup window, select the Trigger tab. Unde

109Chapter 3: Testing PerformanceTo Test the Multi-Card Module5 Set up the Listing window. a In the Listing window, select the Markers tab. b Select

11Chapter 1: General InformationSpecificationsThe specifications are the performance standards against which the product is tested.7KUHVKROG$FFXUDF

110 Chapter 3: Testing PerformanceTo Test the Multi-Card ModuleConnect the logic analyzer 1 Using the 6-by-2 test connectors, connect the logic anal

111Chapter 3: Testing PerformanceTo Test the Multi-Card Module3 Activate the data channels that are connected according to the previous table.a In t

112 Chapter 3: Testing PerformanceTo Test the Multi-Card Module4 Configure the trigger patterna Select the Trigger tab. Under the Trigger tab, selec

113Chapter 3: Testing PerformanceTo Test the Multi-Card ModuleVerify the test signal 1 Check the clock period. Using the oscilloscope, verify that t

114 Chapter 3: Testing PerformanceTo Test the Multi-Card Module2 Check the data pulse width. Using the oscilloscope, verify that the data pulse widt

115Chapter 3: Testing PerformanceTo Test the Multi-Card ModuleCheck the setup/hold combination 1 Select the logic analyzer setup/hold time.a In the

116 Chapter 3: Testing PerformanceTo Test the Multi-Card Module3 Using the Delay mode of the pulse generator channel 1, position the pulses accordin

117Chapter 3: Testing PerformanceTo Test the Multi-Card Module4 Select the clock to be tested. a In the Analyzer setup window select the Sampling ta

118 Chapter 3: Testing PerformanceTo Test the Multi-Card Module5 Verify the test data. a In the Listing window, select Run. The display should show

119Chapter 3: Testing PerformanceTo Test the Multi-Card Moduleb In the Marker Setup window, select the Define... field associated with G1, and the G

12 Chapter 1: General InformationCharacteristicsThe characteristics are not specifications, but are included as additional information.Environmental

120 Chapter 3: Testing PerformanceTo Test the Multi-Card Modulee In the Marker Setup window, select the ‘occurs’ value field that corresponds to mar

121Chapter 3: Testing PerformancePerformance Test RecordPerformance Test Record Performance Test Record$/RJLF$QDO\]HU6HULDO1RBBBBBBB

122 Chapter 3: Testing PerformancePerformance Test Record6LQJOH&ORFN6LQJOH(GJH$FTXLVLWLRQ3DVV)DLO$OO3RGV 6HWXS+ROG7LPH QV -↑ B

123Chapter 3: Testing PerformancePerformance Test Record7HVW 6HWWLQJV 5HVXOWV0XOWLSOHFORFN0XOWLSOHHGJHDFTXLVLWLRQ3DVV)DLO 3DVV)DLO$OO3RGV 6

124 Chapter 3: Testing PerformancePerformance Test Record

1254CalibratingThis chapter gives you instructions for calibrating the logic analyzer.

126 Chapter 4: CalibratingCalibration StrategyThe 16740/41/42A logic analyzer does not require an operational accuracy calibration. To test the modu

1275TroubleshootingThis chapter helps you troubleshoot the module to find defective assemblies.

128 Chapter 5: TroubleshootingThe troubleshooting consists of flowcharts, self-test instructions, a cable test, and a test for the auxiliary power s

129Chapter 5: TroubleshootingTroubleshooting Flowchart 1

13Chapter 1: General InformationRecommended Test EquipmentEquipment Required(TXLSPHQW &ULWLFDO6SHFLILFDWLRQV5HFRPPHQGHG+3$JLOHQW0RGHO3DUW8

130 Chapter 5: TroubleshootingTroubleshooting Flowchart 2

131Chapter 5: TroubleshootingTo run the self-testsSelf-tests identify the correct operation of major, functional subsystems of the module. You can r

132 Chapter 5: TroubleshootingRefer to Chapter 8 in the mainframe service manual for more information on system tests that are not executed. To exit

133Chapter 5: TroubleshootingTo test the cablesThis test allows you to functionally verify the probe cable and probe tip assembly of any of the logi

134 Chapter 5: Troubleshooting3 Set up the Sampling tab. a In the Analyzer setup window, select the Sampling tab.b Select State Mode.c Select Master

135Chapter 5: Troubleshooting4 Assign all pods to Analyzer 1, and configure the pod under test.a Select the Format tab. Under the Format tab, select

136 Chapter 5: Troubleshooting5 Set up the Listing window.a In the Analyzer Setup window, select Window, then select Slot n: Analyzer (where “n” is

137Chapter 5: Troubleshooting7 On the logic analyzer, select Run. The listing should look similar to the figure below. Ignore any error messages dea

138 To test the auxiliary powerThe +5 V auxiliary power is protected by a current overload protection circuit. If the current on pins 1 and 39 excee

1396Replacing AssembliesThis chapter contains the instructions for removing and replacing the logic analyzer module, the circuit board of the module,

14 Chapter 1: General Information

140 Chapter 6: Replacing AssembliesCAUTION: Turn off the instrument before installing, removing, or replacing a module in the instrument.Tools Requi

141Chapter 6: Replacing Assemblies5 Push all other cards into the card cage, but not completely in.This is to get them out of the way for removing a

142 Chapter 6: Replacing AssembliesTo replace the circuit board1 Remove the three screws connecting the probe cables to the back panel, then disconn

143Chapter 6: Replacing AssembliesTo replace the module1 If the module consists of one card, go to step 2.If the module consists of more than one ca

144 Chapter 6: Replacing Assemblies5 Position all cards and filler panels so that the endplates overlap.6 Seat the cards and tighten the thumbscrews

145Chapter 6: Replacing Assembliesordering information.5 Install the screws connecting the probe cable to the rear panel of the module.CAUTION: If y

146 Chapter 6: Replacing AssembliesYou can use either the original shipping containers, or order materials from an Agilent Technologies sales office

1477Replaceable PartsThis chapter contains information for identifying and ordering replaceable parts for your module.

148 Chapter 7: Replaceable PartsReplaceable Parts OrderingParts listedTo order a part on the list of replaceable parts, quote the Agilent Technologi

149Chapter 7: Replaceable PartsAgilent Technologies Sales Office for information.See Also "To return assemblies," page 146.Replaceable Par

152Preparing for UseThis chapter gives you instructions for preparing the logic analyzer module for use.

150 Chapter 7: Replaceable PartsReplaceable Parts5HI'HV $JLOHQW3DUW1XPEHU 47< 'HVFULSWLRQ  ([FKDQJH%RDUG$VVHPEO\

151Chapter 7: Replaceable PartsExploded ViewExploded view of the 16740/41/42A logic analyzer

152

1538Theory of OperationThis chapter presents the theory of operation for the logic analyzer module and describes the self-tests.

154 Chapter 8: Theory of OperationThe information in this chapter is to help you understand how the module operates and what the self-tests are test

155Chapter 8: Theory of Operationsingle ground. For applications where many channels are used (greater than three) and signal risetimes are less tha

156 Chapter 8: Theory of Operationcircuit controls RAM addressing during an acquisition run and during data upload to the mainframe CPU.Test and Clo

157Chapter 8: Theory of OperationThe 16740/41/42A logic analyzer as an expanderThe logic analyzers can be connected together in multi-card master/ex

158 Chapter 8: Theory of OperationTest and Clock Synchronization Circuit. The signals generated by the Test and Clock Synchronization Circuit of the

159Chapter 8: Theory of Operation“1” and “0” is written to the first memory location. The contents of the first memory location is then downloaded a

16 Chapter 2: Preparing for UsePower RequirementsAll power supplies required for operating the logic analyzer are supplied through the backplane con

160 Chapter 8: Theory of OperationChip Registers Read/Write Test. The Chip Registers Read/Write Test verifies that the registers of each acquisition

161Chapter 8: Theory of Operationthat the procedure to test the Time Interval Accuracy in Chapter 3 provides a more reliable characterization of clo

162 Chapter 8: Theory of Operationto see if self-calibration was successful.Passing the Calibration Test implies that the module can reliably perfor

163Chapter 8: Theory of OperationZoom Chip Select Test. The Zoom Chip Select Test verifies that each of the 2GHz TimingZoom memory ICs are individua

164 Chapter 8: Theory of Operation

Index 165Symbols+5 VDC supply, 156Numerics0 V user threshold, 46Aaccessories, 10acquisition, 155, 157acquisition RAM, 155analyzerconnect, 42, 53, 71,

166 IndexTtest0V user threshold, 46analyzer chip memory bus, 160analyzer memory bus SU/H measure, 160cables, 133calibration, 161chip registers, 160co

© Copyright Agilent Technologies 2001All Rights Reserved.Reproduction, adaptation, or translation without prior written permission is prohibited, exce

Product WarrantyThis Agilent Technologies product has a warranty against defects in material and workmanship for a period of one year from date of shi

17Chapter 2: Preparing for Usemechanical defects. If you find any defects, contact your nearest Agilent Technologies Sales Office. Arrangements for

18 Chapter 2: Preparing for Use4 Starting from the top, pull the cards and filler panels that need to be moved halfway out.CAUTION: All multi-card m

19Chapter 2: Preparing for Use

2 The Agilent 16740/41/42A Logic Analyzer—At a GlanceThe Agilent Technologies 16740/41/42A are 400-MHz state/800-MHz timing logic analyzer modules f

20 Chapter 2: Preparing for UseTo configure a multi-card module1 Plan the configuration. Multicard modules can only be connected as shown in the ill

21Chapter 2: Preparing for Use3 Connect a 2x40 cable to J9 and to J10 of each card in the multicard configuration.4 On the expander cards, disconnec

22 Chapter 2: Preparing for Use5 Begin stacking the cards together according to the drawing under step 1. While stacking, connect the free end of th

23Chapter 2: Preparing for Use6 Feed the free end of the 2x10 cables of the lower expander cards through the access holes to the master card. Plug t

24 Chapter 2: Preparing for Use7 Stack the remaining expander boards on top of the master board. While stacking, connect the free end of the 2x40 ca

25Chapter 2: Preparing for Use8 Feed the free end of the 2x10 cables of the expander cards through the access holes to the master card. Plug the 2x1

26 Chapter 2: Preparing for UseTo install the module1 Slide the cards above the slots for the module about halfway out of the mainframe.2 With the p

27Chapter 2: Preparing for Use5 Seat the cards and tighten the thumbscrews.Starting with the bottom card, firmly seat the cards into the backplane c

28 Chapter 2: Preparing for UseTo turn on the system1 Connect the power cable to the mainframe.2 Turn on the instrument power switch.When you turn o

29Chapter 2: Preparing for UseTo clean the module• With the mainframe turned off and unplugged, use mild detergent and water to clean the rear panel

3The 16740/41/42A uses operating system version A.02.50.00 or higher. Agilent Technologies 16700-series mainframes with serial number prefix lower t

30 Chapter 2: Preparing for Use

313Testing PerformanceThis chapter tells you how to test the performance of the logic analyzer against the specifications listed in chapter 1.

32 Chapter 3: Testing PerformanceTo ensure the logic analyzer is operating as specified, software tests (self-tests) and manual performance tests ar

33Chapter 3: Testing PerformanceTo Perform the Self-testsTo Perform the Self-tests There are two types of self-tests: self-tests that automatically

34 Chapter 3: Testing PerformanceTo Perform the Self-testsPerform the self-testsThe self-tests verify the correct operation of the logic analysis sy

35Chapter 3: Testing PerformanceTo Set Up the Test ConnectorsTo Set Up the Test Connectors The test connectors connect the logic analysis system to

36 Chapter 3: Testing PerformanceTo Set Up the Test Connectorse Solder the ground tab of the BNC connector to the center pin of the other row on the

37Chapter 3: Testing PerformanceTo Set Up the Test Connectors2 Build one test connector using a BNC connector and a 17-by-2 section of Berg strip. a

38 Chapter 3: Testing PerformanceTo Set up the Test Equipment and the AnalyzerTo Set up the Test Equipment and the Analyzer Before testing the speci

39Chapter 3: Testing PerformanceTo Set up the Test Equipment and the Analyzerd In the Analyzer<n> Setup window, select the Sampling tab. 4 Set

4 In This BookThis book is the service guide for the 16740/41/42A 200-MHz state/800-MHz timing logic analyzer modules. This service guide has eight

40 Chapter 3: Testing PerformanceTo Test the Threshold AccuracyTo Test the Threshold Accuracy Testing the threshold accuracy verifies the performanc

41Chapter 3: Testing PerformanceTo Test the Threshold AccuracySet up the logic analyzer1 In the Analyzer Setup window, select the Format tab.2 Under

42 Chapter 3: Testing PerformanceTo Test the Threshold AccuracyConnect the logic analyzer1 Using the 17-by-2 test connector, BNC cable, and probe ti

43Chapter 3: Testing PerformanceTo Test the Threshold AccuracyTest the ECL threshold 1 In the Pod Threshold window, select the Standard threshold vo

44 Chapter 3: Testing PerformanceTo Test the Threshold Accuracy3 Using the Modify down arrow on the function generator, decrease offset voltage in 1

45Chapter 3: Testing PerformanceTo Test the Threshold Accuracy4 Using the Modify up arrow on the function generator, increase offset voltage in 1-mV

46 Chapter 3: Testing PerformanceTo Test the Threshold AccuracyTest the 0 V User threshold 1 In the Pod Threshold window, select User Defined. In th

47Chapter 3: Testing PerformanceTo Test the Threshold Accuracy4 Using the Modify up arrow on the function generator, increase offset voltage in 1-mV

48 Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State AcquisitionTo Test the Single-clock, Single-edge, State AcquisitionTes

49Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State Acquisition2 Assign all pods to Analyzer 1.a In the Analyzer setup wind

Contents 51 General InformationAccessories 10Mainframe and Operating System 10Specifications 11Characteristics 12Environmental Characteristics 12Reco

50 Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State Acquisition3 Set up the Format tab. a Under one of the pod fields, sel

51Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State Acquisition4 Set up the Trigger tab.a In the Analyzer setup window, sel

52 Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State Acquisition5 Set up the Listing window. a In the Listing window, selec

53Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State AcquisitionConnect the logic analyzer 1 Using the 6-by-2 test connector

54 Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State Acquisition3 Activate the data channels that are connected according t

55Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State Acquisition4 Configure the trigger pattern.a Select the Trigger tab. Un

56 Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State AcquisitionVerify the test signal 1 Check the clock period. Using the

57Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State Acquisition2 Check the data pulse width. Using the oscilloscope, verify

58 Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State AcquisitionCheck the setup/hold combination 1 Select the logic analyze

59Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State Acquisition3 Using the Delay mode of the pulse generator channel 1, pos

6 ContentsTo Test the Single-clock, Single-edge, State Acquisition 48Set up the equipment 48Set up the logic analyzer 48Connect the logic analyzer 53

60 Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State Acquisition4 Select the clock to be tested. a In the Analyzer setup wi

61Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State Acquisition5 Verify the test data.a In the Listing window, select Run.

62 Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State AcquisitionIf the Label selection field reads Label1_TZ, you must sele

63Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State Acquisition8 Using the Delay mode of the pulse generator channel 1, pos

64 Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State Acquisition9 Select the clock to be tested.a In the Analyzer setup win

65Chapter 3: Testing PerformanceTo Test the Single-clock, Single-edge, State Acquisition12 If the setup/hold used for the previous steps was 4.5/-2.

66 Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State AcquisitionTo Test the Multiple-clock, Multiple-edge, State Acquis

67Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State AcquisitionSet up the logic analyzer Perform the following steps if

68 Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State Acquisition3 Set up the Format tab.a Under one of the pod fields,

69Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State Acquisition4 Set up the Trigger tab. a In the Analyzer setup window

Contents 75 TroubleshootingTo use the flowcharts 128To run the self-tests 131To exit the test system 132To test the cables 133To test the auxiliary p

70 Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State Acquisition5 Set up the Listing window. a In the Listing window, s

71Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State AcquisitionConnect the logic analyzer1 Using the 6-by-2 test connec

72 Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State Acquisition3 Activate the data channels that are connected accordi

73Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State Acquisition4 Configure the trigger pattern.a Select the Trigger tab

74 Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State AcquisitionVerify the test signal1 Check the clock period. Using t

75Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State Acquisition2 Check the data pulse width. Using the oscilloscope, ve

76 Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State AcquisitionCheck the setup/hold with single clock edges, multiple

77Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State Acquisition3 Using the Delay mode of the pulse generator channel 1,

78 Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State Acquisition4 Select the clock combination to be tested.a In the An

79Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State Acquisition5 Verify the test data. a In the Listing window, select

8 Contents

80 Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State AcquisitionIf the Label selection field reads Label1_TZ, you must

81Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State Acquisition8 Using the Delay mode of the pulse generator channel 1,

82 Chapter 3: Testing PerformanceTo Test the Multiple-clock, Multiple-edge, State Acquisition9 Select the clock combination to be tested. a In the A

83Chapter 3: Testing PerformanceTo Test the Single-clock, Multiple-edge, State AcquisitionTo Test the Single-clock, Multiple-edge, State Acquisition

84 Chapter 3: Testing PerformanceTo Test the Single-clock, Multiple-edge, State AcquisitionSet up the logic analyzer Perform the following steps if

85Chapter 3: Testing PerformanceTo Test the Single-clock, Multiple-edge, State Acquisition3 Set up the Format tab. a Under one of the pod fields, se

86 Chapter 3: Testing PerformanceTo Test the Single-clock, Multiple-edge, State Acquisition4 Set up the Trigger tab. a In the Analyzer setup window,

87Chapter 3: Testing PerformanceTo Test the Single-clock, Multiple-edge, State Acquisition5 Set up the Listing window. a In the Listing window, sele

88 Chapter 3: Testing PerformanceTo Test the Single-clock, Multiple-edge, State AcquisitionConnect the logic analyzer1 Using the 6-by-2 test connect

89Chapter 3: Testing PerformanceTo Test the Single-clock, Multiple-edge, State Acquisition3 Activate the data channels that are connected according

91General InformationThis chapter lists the accessories, the specifications and characteristics, and the recommended test equipment.

90 Chapter 3: Testing PerformanceTo Test the Single-clock, Multiple-edge, State Acquisition4 Configure the trigger pattern.a Select the Trigger tab.

91Chapter 3: Testing PerformanceTo Test the Single-clock, Multiple-edge, State AcquisitionVerify the test signal1 Check the clock interval. Using th

92 Chapter 3: Testing PerformanceTo Test the Single-clock, Multiple-edge, State Acquisition2 Check the data pulse width. Using the oscilloscope, ver

93Chapter 3: Testing PerformanceTo Test the Single-clock, Multiple-edge, State AcquisitionCheck the setup/hold with single clock, multiple clock edg

94 Chapter 3: Testing PerformanceTo Test the Single-clock, Multiple-edge, State Acquisition2 Using the Delay mode of the pulse generator channel 1,

95Chapter 3: Testing PerformanceTo Test the Single-clock, Multiple-edge, State Acquisition3 Select the clock to be tested.a In the Analyzer setup wi

96 Chapter 3: Testing PerformanceTo Test the Single-clock, Multiple-edge, State Acquisition4 Verify the test data.a In the Listing window, select Ru

97Chapter 3: Testing PerformanceTo Test the Single-clock, Multiple-edge, State AcquisitionIf the Label selection field reads Label1_TZ, you must sel

98 Chapter 3: Testing PerformanceTo Test the Time Interval AccuracyTo Test the Time Interval AccuracyTesting the time interval accuracy does not che

99Chapter 3: Testing PerformanceTo Test the Time Interval Accuracy3 Set up the function generator according to the following table.Function Generato