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Serial BERT N4906B, Data Sheet V.3
Generator Clock
Figure 13: Block diagram for the clock section
Table 4: Specifications for clock input and 10 MHz reference
input
Interface AC coupled, 50 Ω nominal
Amplitude 200 mV to 2 V
Connector SMA female
The clock of the N4906B provides three different
operation modes:
Internal clock
External clock signal to CLK IN.
10 MHz reference signal to 10 MHz REF IN:
in this mode the internal clock is derived
from the applied 10 MHz reference signal.
•
•
•
Clock frequency range
Clock input and 10 MHz reference input
Trigger output
It operates in two modes: pattern trigger and
divided clock trigger. This provides an electrical
trigger synchronous with the pattern for use with
an oscilloscope or other test equipment. Typically
there is a delay of 32 ns between trigger and data
output when using datarates ≥ 620 Mb/s.
Pattern trigger mode
For PRBS patterns the pulse is synchronized with
a user specified trigger pattern. The repetition rate
is 1 pulse for every 4th pattern.
For memory-based patterns the trigger signal is
synchronized to a certain bit position in the pat-
tern.
Divided clock mode
In divided clock mode the trigger is a square wave
at the clock rate divided by 2, 4, 8, 10, 16, 20, 32,
40, 64, 128.
Table 5: Specification for trigger output
1) 150 MHz to 3.6 GHz external clock, 620 MHz to
3.6 GHz internal clock.
2) Only in combination with option 012.
3) 150 MHz to 12.5 GHz external clock, 620 Mb/s to
12.5 Gb/s internal clock.
4) Unused outputs must be terminated with 50 Ω to
GND.
5) Only option 012 at 10 Gb/s.
6) For positive termination voltage or termination to
GND, external termination voltage must be less than
3 V below VOH. For negative termination volt-age,
external termination voltage must be less than 2 V
below VOH. External termination voltage must be less
than 3 V above VOL.
7) 10 GHz @ 10 kHz offset, 1Hz bandwidth.
8) Recommended for option 003.
Table 2: Clock frequency range
Frequency range
Option 003 150 MHz
1)
to 3.6 GHz
Option 012 9.5 GHz to 12.5 GHz
Option 102
2)
150 MHz
3)
to 12.5 GHz
Pulse width Square wave
Levels High: +0.5 V; Low -0.5 V typ.
Transition times 35 ps typ.
Interface DC coupled, 50 Ω nominal
Connector SMA female
Table 3: Parameters for N4906B serial BERT clock output.
All timing parameters are measured at ECL levels.
Impedance 50 Ω typ.
Amplitude/resolution 0.1 V
pp
to 1.8 V
pp
/ 5 mV
steps
Output voltage window -2.00 to +2.8 V
Short circuit current 72 mA max.
Clock interface
4)
Differential or single-ended,
DC coupled, 50 W
Transition times
20% to 80% < 20 ps typ.
10% to 90% < 25 ps
5)
with N4915A-001 < 50 ps typ.
8)
transition time converter
Addressable technologies LVDS, CML, PECL, ECL
(terminated to 1.3 V / 0 V /
-2 V) low voltage CMOS
External termination -2 V to +3 V
voltage
6)
Jitter 1 ps rms typ.
SSB phase noise
7)
< -75 dBc with internal
clock source
Connector 2.4 mm female
2.4 mm to 3.5 mm adaptors
included
Clock output
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dataTec GmbH
•
Ferdinand-Lassalle-Str. 52
•
72770 Reutlingen
•
Tel. 07121 / 51 50 50
•
Fax 07121 / 51 50 10
•
info@datatec.de
•
www.datatec.de
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