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Table 13: Burst

Non CDR CDR mode

mode

CDR setting time - 2 µs

Synchronisation time

Hardware based PRBS 1536 bits

Memory based pattern 15 kbit

Backlash 1536 bits 1.5 µs

Gate passive time 2560 bits 2560 bits or

1.5 µs

Serial BERT N4906B, Data Sheet V3

Errors Output

This provides an electrical signal to indicate

received errors. The output is the logical ‘OR’ of

errors in a 128-bit segment of the data.

Gating input

If a logical high is applied to the gate input the

analyzer will ignore incoming bits during a BER

measurement. The ignored bit sequence is a multi-

ple of 512 bits.

AUX output

This output can be used to provide either clock or

data signals:

CLOCK: clock signals from the input or recovered

clock signals in CDR mode (option 102)

DATA: data after being compared with the thresh-

old.

Table 11: Specifications for error output

Interface format RZ, active high

Interface DC coupled, 50 Ω nominal

Levels High: 1 V nominal; Low: 0 V

nominal

Pulse width 128 clock periods

Connector SMA female

Table 14: Specifications of AUX output

Interface AC coupled, 50 Ω nominal

Amplitude 600 mV nominal

Connector SMA female

Table 12: Specification for gating input

Interface levels DC coupled, 50 Ω nominal

Levels TTL compatible

Connector SMA female

Pulse width 256 clock periods

For measuring data in bursts of bits, rather than

one continuous stream of bits, a special operating

mode is used. This is the burst sync mode. In this

case, the signal at the gating input controls the

timing of synchronization and error counting for

each burst. This is an important feature for recir-

culation loop measurements.

If the clock data recovery (CDR) is used to recover

the clock out of the burst data, the CDR needs the

first bits of the burst data to settle. The number of

bits the systems needs to synchronize itself during

a burst depends on wether the pattern consists of

hardware based PRBS data or memory based data.

To run properly in burst mode the system requires

a backlash of data after the gate input returned

to high. During each burst the gate input has to

remain passive for a certain time.

Figure 18: Burst mode

1) Depends on when and how often the unique word for syn-

chronistation occurs.

2) Whichever takes longer.

dataTec GmbH

•

Ferdinand-Lassalle-Str. 52

•

72770 Reutlingen

•

Tel. 07121 / 51 50 50

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Fax 07121 / 51 50 10

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info@datatec.de

•

www.datatec.de

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