11
Serial BERT N4906B, Data Sheet V.3
Error Detector
Figure 17: Front view error detector
The error detector compares each individual bit
against the expected data (deterministic data or
data pattern) in real time. The incoming bits must
be periodic.
Features:
Data input: normal / inverted
Differential data inputs (option 101 or 103)
Variable clock / data sampling delay
Clock / data auto-alignment
0/1 decision threshold auto-alignment
Clock data recovery (CDR) for selected
Frequency ranges or ext. clock (option 102)
Data input
•
•
•
•
•
•
•
Clock input
The error detector needs either an external clock
signal or a recovered clock signal (option 102
CDR).
The CDR works with specified PRBS patterns up to
2
31
-1. The CDR expects a DC balanced pattern. The
CDR expects a transition density of one transition
for every second bit.
Clock divider 4, 8, 16 up to 11 Gb/s
32, 40, 64, 128 up to 12.5 Gb/s
Interface DC coupled, 50 Ω nominal
Levels High: + 0.5 V; Low: - 0.5 V
Minimum pulse width Pattern length x clock period/2
e.g. 10 Gb/s with 1000 bits = 50 ns
Connector SMA female
Table 8: Parameters for N4906B error detector
Range of operation
Option 003 150 Mb/s to 3.6 Gb/s
Option 012 9.5 Gb/s to 12.5 Gb/s
Option 102
1)
150 Mb/s to 12.5 Gb/s
Inputs
3)7)
normal/inverted Single-ended: 50 Ω, typ.
Differential
4)
: 100 Ω typ.
Format NRZ
Max input amplitude 2.0 V
Termination voltage
3)
-2 V to +3V or off
(true differential mode
4)
)
Sensitivity
5)
< 50 mV
pp
Decision threshold range -2 V to +3 V in 0.1 mV
steps
Max levels -2.2 V to +3.2 V
Phase margin
6)
1 UI - 12 ps typ.
Clock/data sampling delay ±0.75 ns in 100 fs steps
Connector 2.4 mm female
2.4 mm to 3.5 mm adapters
included
Table 9: Specification clock input
Frequency range
Option 003 150 MHz to 12.5 GHz
Option 012 9.5 GHz to 12.5 GHz
Option 102
1)
150 MHz to 12.5 GHz
Interface AC coupled, 50 Ω nominal
Amplitude 100 mV to 1.2 V
Sampling Positive or negative clock
edge
Connector SMA female
CDR output jitter
2)
0.01 UI rms typ.
Clock data recovery
2)
Loop bandwidth (typ.)
(CDR)
9.9 Gb/s to 10.9 Gb/s 8 MHz
4.23 Gb/s to 6.40 Gb/s 4 MHz
2.115 Gb/s to 3.20 Gb/s 2 MHz
1.058 Gb/s to 1.6 Gb/s 1 MHz
Table 10: Specifications for trigger output
1) Only in combination with option 012.
2) Only with option 102.
3) User has to define a 2 V operating voltage window, which is
in the range between -2.0 V to +3.0 V. Data signals, termi-
nation voltage and decision threshold have to be within this
voltage window.
4) If option 101 or option 003 is installed.
5) @ 10 Gb/s, BER 10-12, PRBS 2
31
-1.
6) Based on internal clock.
7) Unused inputs should be terminated with 50 Ω to GND.
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Trigger out
Pattern trigger mode
This provides an electrical trigger synchronous
with the selected error detector reference pattern.
In pattern mode the pulse is synchronized to rep-
etitions of the output pattern. For PRBS patterns
the repetition rate is 1 pulse for every 4th pattern
repetition
Divided clock mode
In divided clock mode the trigger signal is a square
wave.
dataTec GmbH
•
Ferdinand-Lassalle-Str. 52
•
72770 Reutlingen
•
Tel. 07121 / 51 50 50
•
Fax 07121 / 51 50 10
•
info@datatec.de
•
www.datatec.de
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