Agilent Technologies 8000 Series Manual do Utilizador Página 2

  • Descarregar
  • Adicionar aos meus manuais
  • Imprimir
  • Página
    / 10
  • Índice
  • MARCADORES
  • Avaliado. / 5. Com base em avaliações de clientes
Vista de página 1
A Better Way – Collaborative
development between Agilent and
Xilinx have produced a faster and
more effective way to use your
logic analyzer to debug FPGAs
and the surrounding system. The
Agilent FPGA dynamic probe,
used in conjunction with an
Agilent MSO, provides the most
effective solution for simple
through complex debugging.
View internal activity – With the
digital channels on your MSO, you
are normally limited to measuring
signals at the periphery of the
FPGA. With the FPGA dynamic
probe, you can now access signals
internal to the FPGA. You can
measure up to 64 internal signals
for each external pin dedicated
to debug, unlocking visibility into
your design that you never had
before.
Make multiple measurements in
seconds – Moving probe points
internal to an FPGA used to be
time consuming. Now, in less than
a second, you can easily measure
different sets of internal signals
without design changes. FPGA
timing stays constant when you
select new sets of internal signals
for probing.
Leverage the work you did in your
design environment – The FPGA
dynamic probe maps internal
signal names from your FPGA
design tool to your Agilent MSO.
Eliminate unintentional mistakes
and save hours of time with this
automatic setup of signal and bus
names on your MSO.
Board
JTAG
Xilinx JTAG Cable
Parallel
or USB
FPGA
Probe outputs
on FPGA pins
SW application supported
by all Infiniium MSOs.
ATC2
Insert ATC2 core with
Xilinx Core Inserter
Figure 2. Create a timesaving FPGA measurement system. Insert an ATC2 (Agilent
Trace Core) core into your FPGA design. With the application running on your MSO
you control which group of internal signals to measure via JTAG.
To FPGA pins
Selection MUX
1-128
1-128
1-128
Select
1-128
JTAG
1-128
Change signal bank
selection via JTAG
Figure 3: Access up to 64 internal signals for each debug pin. Signal banks all have
identical width (1 to 128 signals wide) determined by the number of device pins you
devote for debug. Each pin provides sequential access to one signal from every input bank.
Debug your FPGAs faster and more effectively with a MSO
2
Vista de página 1
1 2 3 4 5 6 7 8 9 10

Comentários a estes Manuais

Sem comentários