Agilent Technologies J-BERT N4903B Manual do Utilizador descarregar pdf (Página 12)

Error add input (ERROR ADD)

The external error add input adds a single error to the data output

for each rising edge at the input. When electrical idle is selected

for the data and aux data outputs: a logical high state causes

the output to transition to electrical idle state. A logic low state

causes the outputs to return to normal operation.

Table 6. Speciﬁcations for error inject input

Levels TTL compatible

Interface DC coupled, 50 Ω nominal

Connector SMA female

10 MHz reference output (10 MHZ REF OUT)

Table 7. Speciﬁcations for the 10 MHz reference output

Amplitude 1 V into 50 Ω typical

Interface AC coupled,

50  output impedance

Connector BNC, rear panel

Speciﬁcations-Pattern Generator

Table 8. Speciﬁcations for trigger/reference clock output

Pulse width Square wave

Amplitude/ resolution 0.050 V to 1.800 V, 5 mV steps.

Addresses LVDS, CML, PECL, ECL

(terminated to 1.3V/0 V/-2 V), low

voltage CMOS

Output voltage window - 2.0 V to +3.0 V

Predefined levels ECL, PECL (3.3V), LVDS, CML

Transition times < 20 ps typical (20% to 80%)

< 25 ps typical (10% to 90%)

Interface

DC coupled, 50 Ω nominal,

Single ended or differential

Connector 2.4 mm female

1. Unused output must be terminated with 50 Ω to GND.

AUX input (AUX IN)

When the alternate pattern mode is activated, the memory is split

into two parts, and the user can define a pattern for each part.

Depending on the operating mode of the auxiliary input, the user

can switch the active pattern in real time by applying a pulse

(mode 1) or a logical state (mode 2) to the auxiliary input. If the

alternate pattern mode is not activated, the user can suppress the

data on the data output by applying a logical high to the auxiliary

input (mode 3).

Table 9. Speciﬁcations for auxilliary input

Levels TTL compatible

Interface DC coupled, 50 Ω nominal

Connector SMA female

Trigger/reference clock outputs

(TRIGGER/ REF CLK OUT)

This output provides a trigger signal synchronous with the

pattern, for use with an oscilloscope or other test equipment.

Typically there is a delay of 32 ns between trigger and data output

for data rates > 620 Mb/s. The trigger output has two modes.

Pattern trigger mode: For PRBS patterns; the pulse is synchro-

nized with a user specified trigger pattern. One pulse is generated

for every 4th PRBS pattern.

Divided clock mode: Generates a square wave (clock) with the

frequency of the full-rate clock divided by 2, 4, 8, 10, 16, 20, 24,

25, 26, up to 32,792 . It is possible to enable/disable SJ, SSC or

residual SSC for this output to use it as a lower frequency

reference clock.

Auxillary clock output (AUX CLK OUT)

This output is intended as clock input for N4916B de-emphasis

signal converter and the 28 Gb/s 2:1 multiplexer N4876A.

Table 10. Speciﬁcations for auxillary clock output

Output level > 150 mV typical

Clock signal Full-rate

Interface AC coupled, 50  nominal

Connector SMA female

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 25 26

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