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Pattern Generator Speciﬁcations

Clock output (CLK OUT)

Clock can operate at full bit-rate or at half bit-rate (Option 003) to

support testing of forward clocked devices.

Table 3. Clock output speciﬁcations

Frequency range 150 MHz to 14.2 GHz (Option D14,

in addition to C13 or G13);

150 MHz to 12.5 GHz (Option C13 or G13);

can be programmed up to 13.5 GHz

150 MHz to 7 GHz (Option C07 or G07);

< 620 MHz only with external clock

Half-rate clocking Only with Option 003: Available at bit rates

> 2.7 Gb/s; duty cycle on half-rate clock

adjustable 40% to 60%

Amplitude/resolution 0.050 V pp to 1.800 V pp, 5 mV steps

Output voltage window -2.00 to +3.00 V

Transition times

20% to 80%

10% to 90%

< 20 ps

< 25 ps

External termination

voltage

-2 V to +3 V

Jitter 800 fs rms typical with internal clock

SSB phase noise < -75 dBc with internal clock source, 10 GHz

at 10 kHz offset, 1 Hz bandwidth

Interface

Differential or single-ended, DC coupled,

50 Ω output impedance

Connector 2.4 mm female

1. At 10 Gb/s and 7 Gb/s

2. For positive termination voltage or termination to GND, external termination

voltage must be less than 3 V below VOH. For negative termination voltage,

external termination voltage must be less than 2 V below VOH. External

termination volt age must be less than 3 V above VOL.

3. Unused outputs must be terminated with 50 Ω to GND.

Clock input (CLK IN)

There are two modes when using the clock input connector.

1. External clock mode: all output signals follow the external

clock and its modulation. The modulation of the external clock

must be within the same range given for SSC and SJ (see

Table 12). If the external clock is above 6.75 GHz, all internal

jitter sources can be used (for using 610 ps delay line, external

clock divider z = 4). Below 6.75 GHz, SJ and SSC are not avail-

able. However, the external clock can optionally be divided by

1, 2, 4, 8, or 16, provided that the resulting bit rate does not fall

below 150 Mb/s. Modulation using the 220 ps delay line is still

available (see Figure 22).

2. External PLL mode: it is used to lock the generator to an

external clock. The provided clock must not be modulated in

external PLL mode. All internal jitter sources are available. A

clock multiplication with x/y is possible, with x, y = 1,2,3, to

255. The resulting bit rate has to be within the range 620 Mb/s

to maximum bit rate.

E xte rn al clock

10 M H z re f clock

Interna l cloc k

E xte rn al clock

(P L L m o de )

C loc k ge nera tor

z = 1,2,4,8,16,

resulting bit rate

must be > 150 Mb/s

VCOVCO

PLLPLL

1/z1/z

Clock

source

selection

x/y

Figure 16. N4903B supports multiple clock modes

10 MHz reference input (10 MHz REF IN)

This is used to lock the generator to an external 10 MHz reference

clock. The data rate can be selected within the same range as if

the internal clock would be used. The provided reference clock

must not be modulated. All internal jitter sources are available.

Table 4. Speciﬁcations for clock input and 10 MHz reference input

Amplitude 200 mV to 2 V

Frequency CLK IN: 150 MHz to 12.5 GHz

(14.2 GHz for Option D14)

10 MHz REF IN: 10 MHz

Interface AC coupled, 50  nominal

Connectors

Clock input

10 MHz reference input

SMA female, front panel

BNC, rear panel

Delay control input (DELAY CTRL IN)

The external signal applied to delay control input varies the delay

between data output and clock output. This can be used to gener-

ate jittered signals to stress the device under test in addition to

the calibrated jitter injection from N4903B.

Table 5. Speciﬁcations for delay control input

Range -110 ps to +110 ps

Sensitivity Typical

Linearity ±5% typical

Modulation bandwidth 1 GHz typical at 10.8 Gb/s

data rate

Levels -275 mV to +275 mV

Interface DC coupled, 50  nominal

Connector SMA female

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 25 26

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