Agilent Technologies J-BERT N4903B Manual do Utilizador descarregar pdf (Página 2)

The de-emphasis technique is used in many popular gigabit serial bus inter-

faces operating at data rates above 1Gb/s, i.e. PCI Express

, USB3, SATA,

10GBASE-KR, 40GBASE-KR4, QPI, Hypertransport, memory buses.

Analyze error, jitter or eye performance of devices using half-rate

clocks

Half-rate clocks are used in some of the highest performance serial bus inter-

faces, such as front-side buses QPI and Hypertransport, or memory buses.

By using the N4916B’s clock multiplier (Option 001), an external clock is

provided, to use the analyzer of J-BERT N4903B can be used to accurately

characterize the error, eye, jitter performance without using a CDR.

The de-emphasis technique is used in many high-speed serial bus interfaces to

compensate for signal distortions caused by the transmission of multi-gigabit

electrical signals over PC board traces. With data rates moving beyond 5

Gb/s the simple 2-tap de-emphasis is more and more replaced by 3- or 4-tap

de-emphasis techniques, i.e. for front-side buses such as QPI, HT, or 10GBASE

KR backplanes. The new N4916B de-emphasis signal converter enables

R&D and test engineers to accurately emulate transmitter de-emphasis with

adjustable 4-tap de-emphasis levels, while being transparent to jitter even on

non-balanced pattern streams. It can also be used to compensate for distortions

caused by cables, fixtures or testboards in the test set up.

Figure 1. Differential signal with variable

de‑emphasis on 1 pre‑cursor and 2 post‑cursors

generated by N4916B

Agilent N4916B Applications

Accurately emulate 4-tap de-empashis

1 1 1 1 0 0 0 0 1 1

1 2 3 4 5 6 7 8

Sem comentários

Agilent Technologies J-BERT N4903B Manual do Utilizador Página 2