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Chapter 12 249

Peripheral Devices

N5102A Digital Signal Interface Module

Clock Timing for Parallel Interleaved Data

The N5102A module provides the capability to interleave the digital I and Q samples. There are two

choices for interleaving:

• IQ, where the I sample is transmitted first

• QI, where the Q sample is transmitted first

When parallel interleaved is selected, all samples are transmitted on the I data lines. This effectively

transmits the same number of samples during a sample period on half the number of data lines as

compared to non-interleaved samples. (A sample period consists of an I and Q sample.) Clocks per

sample is still a valid parameter for parallel interleaved transmissions and creates a reduction in the

sample rate relative to the clock rate. The clocks per sample selection is the ratio of the reduction.

Figure 12- 5 shows each of the clocks per sample selections, for a parallel IQ interleaved port

configuration, using a word sized of four bits and the clock timing relative to the I and Q samples.

For a parallel QI interleaved port configuration, just reverse the I and Q sample positions. For input

mode, the clocks per sample setting is always one.

Figure 12-5 Clock Timing for a Parallel IQ Interleaved Port Configuration

Q sample

4 bits per word

I sample

4 bits per word

1 Sample Period

1 Clock Per Sample

1 Clock

The I sample is transmitted on one clock transition and the Q sample is transmitted on the

Clock

other transition; the sample and clock rates are the same.

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Agilent Technologies E8257C PSG Guia do Utilizador Página 263