Table 11: Specifications for error detector
Range of operation 150 Mb/s to 12.5 Gb/s
(opt. C13)
150 Mb/s to 7 Gb/s
(opt. C07)
Format NRZ
Maximum input amplitude 2.0 V
Termination voltage
1)
-- 2 V to +3 V or off
(true differential mode)
Sensitivity
2)
< 50 mV pp
Intrinsic transition time
4)
25 ps typical 20% to 80%,
single ended
Decision threshold range --2 V to +3 V in 1 mV steps
Maximum levels --2.2 V to +3.2 V
Phase margin
3)
1 UI – 12 ps typical
Clock/Data sampling delay ± 0.75 ns in 100 fs steps
Interface Single-ended: 50 Ω nominal,
Differential: 100 Ω nominal
Connector 2.4 mm female
1)
Selectable 2V operating voltage window, which is in the
range between --2.0 V to +3.0 V. The data signals, termination
voltage and decision threshold have to be within this voltage
window.
2)
At 10 Gb/s, BER 10
-12
, PRBS 2
31
-1.
3)
Based on the internal clock.
4) At cable input, @ ECL levels
10 J-BERT N4903A High-Performance Serial BERT Data Sheet
Error detector key characteristics:
• True differential inputs to match today’s ports
• Built-in CDR for clock-less data
• Auto-alignment of sampling point
• Bit Recovery Mode for unknown data traffic (opt. AO1)
• Burst Mode for testing recirculation loop
• BER result and Measurement suite
• Quick eye diagram
• Pattern capture
• CDR with tunable loop bandwith (opt. UTR)
Table 12: Specification for the clock input
Frequency range 150 MHz to 12.5 GHz
(option C13)
150 MHz to 7 GHz
(option C07)
Amplitude 100 mV to 1.2 V
Sampling Positive or negative
clock edge
CDR output jitter 0.01 UI rms typical
Clock data recovery (CDR) Loop bandwidth
1)
typical
9.2 Gb/s to 11.32 Gb/s 8 MHz
4.23 Gb/s to 6.40 Gb/s 4 MHz
2.115 Gb/s to 3.20 Gb/s 2 MHz
1.058 Gb/s to 1.6 Gb/s 1 MHz
Interface AC coupled, 50 Ω nominal
Connector SMA female
1)
The CDR works with specified PRBS patterns up to 2
31
-1. The
CDR expects a DC balanced pattern and a transition density of 50%.
Figure 15: Front panel connectors for error detector.
Error Detector Specifications
Please note: Options and capabilities described in ITALIC are
preliminary.
Table 13: Preliminary specifications for CDR with tunable loop
bandwidth (N4903A option UTR)
Data rate range 1 Gb/s to 12.5 Gb/s.
(opt. C13)
1)
1 Gb/s to 7 Gb/s (opt. CO7)
Tunable loop bandwidth 100 kHz to 12 MHz
Compliant CDR settings for PCIe, SATA, FC, FB-DIMM,
CEI, 10 GbE/XAUI, XFP/XFP
Tolerates SSC
1
) With bit recovery mode enabled the max. data rate is 11.5 Gb/s
BER Result Display
The N4903A error detector measures:
1. BER
2. Accumulated BER results
• Accumulated errored O’s and 1’s
• G.821
• Error-free intervals
• Accumulated parameters
• Burst results
3. Eye results
Eye Diagram Result Display
• 1-/0- level
• Eye height/amplitude/width
• Jitter p-p and rms
• Cross voltage
• Signal to noise ratio
• Duty cycle distortion
• Extinction ratio
Data Inputs (DATA IN)
Clock Inputs (CLK IN)
The error detector requires an external clock signal
to sample data or it can recover the clock from the
data signal using the built-in clock data recovery
(CDR).
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